1. Technical Field
The present invention relates in general to a test system for testing integrated circuit Devices Under Test (DUTs). More particularly, the present invention relates to a system for effective reception of low power signals transmitted from a DUT through the wafer test system.
2. Related Art
FIG. 1 shows a simplified block diagram of a typical test system for testing DUTs on a semiconductor wafer. The test system includes a test controller or tester 4 connected by a communication cable 6 to a test head 8 and probe card 18. The test system further includes a prober made up of a stage 12 for mounting a wafer 14 being tested, the stage 12 being moved into contact with probes 16 on the probe card 18, the probes 16 for contacting pads of the DUTs formed on the wafer. Examples of the probes 16 include resilient spring probes, pogo pins, cobra type probes, conductive bumps or other forms of probes for contacting DUTs that are known in the art. Cameras 20 and 22 are shown attached to the prober stage 12 and the test head 8 to enable precise alignment of the probes 16 with contacts of DUTs formed on the wafer 14.
In the test system, test data is generated by the test controller 4 and transmitted through the communication cable 6 to the test head 8. Test results are then provided from DUTs on the wafer through the test head 8 back to the test controller 4. The test head 8 contains a set of test channels. Typically test data provided from the test controller 4 is provided through individual tester channels through the cable 6 that are separated in the test head 8 so that each channel is carried through the probe card 18 to a separate one of the probes 16. The channels are linked from the test head 8 to the probe card 18 by electrical connections 24.
Each of the probes 16 typically contacts a single input/output (I/O) terminal or pad on a DUT of the wafer 14 being tested. Each tester channel can either transmit a test signal to a DUT input or monitor a DUT output signal to determine whether the IC is behaving as expected.
FIG. 2 shows details illustrating a channel 31 provided between the test controller 4 and a DUT 351. As shown, the test controller 4 for the channel 31 shown includes a bi-directional buffer with an output buffer portion 30 connecting to channel line 31 to transmit signals, and an input buffer portion 32 receiving signals from line 31. As in FIG. 1, the channel line 31 of FIG. 2 is provided from the test controller 4 through test head 8, connectors 24, probe card 18, and one of probes 14 to a pad on a DUT 351. The channel line 31 is shown as a 50 Ohm line typically set to match the impedance to and from the test system. Once testing is complete, the wafer is diced up to separate the DUTs 351-353.
A drawback to the test system illustrated in FIGS. 1 and 2 is that a DUT output signal in some cases will not have sufficient power to adequately drive the 50 Ohm line interface to the tester. It would be desirable to provide a test system that can test signals from a DUT in one direction, including low power signals that cannot drive a 50 Ohm test line, while simultaneously providing a signal path from the tester to the DUT in the reverse direction. Another key requirement of such an interface is to not interfere with DC parametric measurements, such as leakage test measurements, made by the test system.